1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a CMOS transistor and a method of fabricating the same. Although the present invention has a wide range of applications, it is particularly suitable for highly integrated circuits.
2. Discussion of the Related Art
In general, a complementary metal oxide semiconductor (CMOS) transistor has a P channel transistor and an N channel transistor on a substrate. For example, the CMOS transistor used for an SRAM cell is made by forming an NMOS bulk transistor on a substrate and then forming a PMOS thin film transistor thereon. The productivity or yield of the CMOS transistor is low because of its numerous processes. Therefore, there is now required a CMOS transistor allowing high integration with a simple process for an SRAM cell which forms the PMOS transistor serving as a load transistor in the form of a thin film transistor, and the NMOS bulk transistor serving as a drive transistor.
With reference to the attached drawings, a conventional CMOS transistor will be described below.
As illustrated in FIG. 1, a conventional CMOS transistor forms an NMOS bulk transistor by depositing a gate oxide layer 3 and a gate electrode 4 (in this order) on the active region of a substrate 1 electrically isolated by a field insulation layer 2. A silicon oxide layer, as an interlevel insulation layer 5, is deposited on the overall surface of the substrate 1 including the gate electrode 4 of the NMOS bulk transistor. A gate electrode 6 of the PMOS TFT is formed on a predetermined portion of the interlevel insulation layer 5, and a gate oxide layer 7 is formed on the gate electrode 6 of the PMOS TFT. A polysilicon body layer 8 of the PMOS TFT is formed on the gate oxide layer 7 over the gate electrode 6 of the PMOS TFT. A source region 8a and a drain region 8b are formed in both sides of the polysilicon body layer 8 on the gate oxide layer 7.
However, the thus-structured device has a problem in that the process of stacking the PMOS TFT on the NMOS bulk transistor requires too many steps, thereby decreasing its productivity and increasing cost.